Japanese chemical giant Resonac Corporation officially opened a new U.S. research center dedicated to advanced semiconductor packaging on May 5, 2024, in the San Francisco Bay Area, marking the full-scale launch of a 12-company international consortium aimed at accelerating next-generation chip assembly technologies.

The US-JOINT consortium, led by Resonac Corporation, unites 12 Japanese and U.S. materials and equipment manufacturers in a shared mission: to dramatically shorten the time from concept to commercial-ready packaging technology.

The facility, located in Union City’s East Bay, represents what Resonac describes as its first U.S. research center dedicated to advanced semiconductor packaging, establishing a key component of the AI supply chain in the region.

Hidehito Takahashi, President and CEO of Resonac, said in a company statement that the consortium aims to compress concept verification cycles from approximately six months to as little as one month by enabling participating companies to conduct development closer to Silicon Valley customers, including major cloud computing providers.

“Through collaboration between semiconductor-related companies from Japan and the United States, the initiative will accelerate global semiconductor innovation,” Takahashi said in prepared remarks.

The consortium brings together major industry players including KLA Corporation, Kulicke and Soffa Industries, Namics Corporation, Tokyo Ohka Kogyo, Toppan Inc., TOWA Corporation, Ulvac Inc., 3M Company, and Resonac itself, according to company announcements.

Industry executives have expressed support for the collaborative approach at the facility’s opening ceremony, which drew government officials and industry leaders from both countries.

“Collaborative efforts like US-JOINT address important industry needs,” said a Broadcom spokesperson in a statement to The Wire & Dispatch. “We look forward to seeing how this initiative can contribute to accelerating semiconductor innovation in the region.”

AMD similarly expressed interest in the consortium’s work. “With US-JOINT now operational in the Bay Area, we expect increased technical collaboration to lead to more efficient joint development,” an AMD representative said. “We welcome efforts that can strengthen ecosystem collaboration.”

The facility’s strategic positioning reflects the growing importance of advanced packaging in the current AI chip boom. According to the Japan Ministry of Economy, Trade and Industry, “The expansion of generative AI and current computing demands require more advanced packaging solutions.”

The new R&D hub focuses on the critical stage where bare silicon wafers are transformed into stacked, high-performance modules that power AI servers, data center hardware, and smartphones. Union City officials say the facility is expected to bring new jobs and strengthen technical ties between Bay Area chip customers and Japanese suppliers.

The consortium’s emphasis on proximity to customers addresses a noted gap in the U.S. semiconductor supply chain. Asia has traditionally dominated advanced packaging and back-end semiconductor processing. Through the US-JOINT program, semiconductor device makers in the region hope to advance domestic capabilities in substrate, interposer and package fabrication technologies.

The consortium’s R&D center features cleanrooms rated at Class 100 and Class 1,000, along with advanced semiconductor packaging process tools covering patterning, bonding, molding, and plating, plus evaluation and analysis equipment, according to Resonac specifications.

The facility is designed to serve fabless companies, semiconductor manufacturers, and engineers from member companies conducting collaborative research projects.

The facility’s opening comes as the semiconductor industry experiences significant growth driven by AI demand. According to the Semiconductor Industry Association, the global semiconductor market grew 21.6% in 2023, reaching $574 billion. Data center and AI applications have become key growth drivers, with logic and memory chips seeing particularly strong demand.

Advanced packaging has emerged as a critical focus area as chipmakers work to integrate more computing power into smaller form factors. The technology supports growth in key sectors including artificial intelligence and autonomous driving applications. New packaging concepts are gaining importance as major technology companies and cloud providers design custom AI semiconductors.

The opening follows two years of preparatory work by consortium partners to establish the center’s operations, develop research protocols, and build collaborative frameworks across participating companies. With the facility now operational, the consortium plans to begin proof-of-concept projects spanning advanced materials, packaging evaluation methods, and integration technologies tailored to AI and high-performance computing applications.

For the broader Bay Area technology ecosystem, the facility represents both validation of the region’s continued importance to global technology development and a strategic development in the ongoing competition for semiconductor supply chain advantages. The consortium’s work could influence broader industry trends toward regionalized semiconductor packaging capabilities.

Partners are expected to announce additional projects and collaborations in the coming months as initial research projects progress from early validation phases toward pilot production and potential expansion of local operations and hiring.

The US-JOINT facility represents part of broader efforts by Japanese and American companies to strengthen semiconductor supply chain cooperation amid growing global competition in critical technology sectors.